Memory Device Having Electrically Floating Body Transistor

ABSTRACT

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

CROSS-REFERENCE

This application claims the benefit of co-pending U.S. Provisional Application No. 61/621,546 filed Apr. 4, 2012, which application is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to semiconductor memory technology. More specifically, the present invention relates to a semiconductor memory device having an electrically floating body transistor.

BACKGROUND OF THE INVENTION

Semiconductor memory devices are used extensively to store data. Memory devices can be characterized according to two general types: volatile and non-volatile. Volatile memory devices such as static random access memory (SRAM) and dynamic random access memory (DRAM) lose data that is stored therein when power is not continuously supplied thereto.

A DRAM cell without a capacitor has been investigated previously. Such memory eliminates the capacitor used in the conventional 1T/1C memory cell, and thus is easier to scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell. Chatterjee et al. have proposed a Taper Isolated DRAM cell concept in “Taper Isolated Dynamic Gain RAM Cell”, P. K. Chatterjee et al., pp. 698-699, International Electron Devices Meeting, 1978 (“Chatterjee-1”), “Circuit Optimization of the Taper Isolated Dynamic Gain RAM Cell for VLSI Memories”, P. K. Chatterjee et al., pp. 22-23, IEEE International Solid-State Circuits Conference, February 1979 (“Chatterjee-2”), and “dRAM Design Using the Taper-Isolated Dynamic RAM Cell”, J. E. Leiss et al., pp. 337-344, IEEE Journal of Solid-State Circuits, vol. SC-17, no. 2, April 1982 (“Leiss”), which are hereby incorporated herein, in their entireties, by reference thereto. The holes are stored in a local potential minimum, which looks like a bowling alley, where a potential barrier for stored holes is provided. The channel region of the Taper Isolated DRAM cell contains a deep n-type implant and a shallow p-type implant. As shown in “A Survey of High-Density Dynamic RAM Cell Concepts”, P. K. Chatterjee et al., pp. 827-839, IEEE Transactions on Electron Devices, vol. ED-26, no. 6, June 1979 (“Chatterjee-3”), which is hereby incorporated herein, in its entirety, by reference thereto, the deep n-type implant isolates the shallow p-type implant and connects the n-type source and drain regions.

Terada et al. have proposed a Capacitance Coupling (CC) cell in “A New VLSI Memory Cell Using Capacitance Coupling (CC) Cell”, K. Terada et al., pp. 1319-1324, IEEE Transactions on Electron Devices, vol. ED-31, no. 9, September 1984 (“Terada”), while Erb has proposed Stratified Charge Memory in “Stratified Charge Memory”, D. M. Erb, pp. 24-25, IEEE International Solid-State Circuits Conference, February 1978 (“Erb”), both of which are hereby incorporated herein, in their entireties, by reference thereto.

DRAM based on the electrically floating body effect has been proposed both in silicon-on-insulator (SOI) substrate (see for example “The Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures”, Tack et al., pp. 1373-1382, IEEE Transactions on Electron Devices, vol. 37, May 1990 (“Tack”), “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002, all of which are hereby incorporated herein, in their entireties, by reference thereto) and in bulk silicon (see for example “A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM”, R. Ranica et al., pp. 128-129, Digest of Technical Papers, 2004 Symposium on VLSI Technology, June 2004 (“Ranica-1”), “Scaled 1T-Bulk Devices Built with CMOS 90 nm Technology for Low-Cost eDRAM Applications”, R. Ranica et al., 2005 Symposium on VLSI Technology, Digest of Technical Papers (“Ranica-2”), “Further Insight Into the Physics and Modeling of Floating-Body Capacitorless DRAMs”, A. Villaret et al, pp. 2447-2454, IEEE Transactions on Electron Devices, vol. 52, no. 11, November 2005 (“Villaret”), “Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrate”, R. Pulicani et al., pp. 966-969, 2010 17^(th) IEEE International Conference on Electronics, Circuits, and Systems (ICECS) (“Pulicani”), all of which are hereby incorporated herein, in their entireties, by reference thereto).

Widjaja and Or-Bach describes a bi-stable SRAM cell incorporating a floating body transistor, where more than one stable state exists for each memory cell (for example as described in U.S. Patent Application Publication No. 2010/00246284 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”) and U.S. Patent Application Publication No. 2010/0034041, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), which are both hereby incorporated herein, in their entireties, by reference thereto). This bi-stability is achieved due to the applied back bias which causes impact ionization and generates holes to compensate for the charge leakage current and recombination.

As memory cells are being scaled to smaller feature size, the variability in memory cells characteristics also increase, for example due to the Random Dopant Fluctuation (RDF). A purpose of this invention is to provide an improvement of the variability of memory cells characteristics.

SUMMARY OF THE INVENTION

In one aspect of the present invention, a semiconductor memory cell comprises: a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; a gate positioned between the first and second regions; and a back-bias region configured to generate impact ionization when the memory cell is in one of the first and second states, and wherein the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

In at least one embodiment, the memory cell further comprises a substrate region, wherein the back-bias region is positioned between the substrate region and the floating body region.

In at least one embodiment, the floating body region comprises first and second subregions, wherein the first subregion has a first doping concentration level and the second region has a second doping concentration level, and wherein the first doping concentration is different from the second doping concentration level.

In at least one embodiment, the first and second subregions have the same conductivity type.

In at least one embodiment, the first subregion is further from the back-bias region than a distance from the second subregion to the back bias region, and wherein the second doping concentration level is greater than the first doping concentration level.

In at least one embodiment, the floating body region further comprises a third subregion, the third subregion having a third doping concentration level, wherein the third doping concentration level is different from at least one of the first and second doping concentration levels.

In at least one embodiment, the first subregion is furthest from the back-bias region, relative to the second and third subregions, and the first doping concentration level is lowest relative to the second and third doping concentration levels.

In at least one embodiment, the memory cell the first and second subregions are localized so that they do not underlie the first and second regions.

In at least one embodiment, the memory cell further comprises at least one halo region adjacent to at least one of the first and second regions, wherein each halo region comprises a first conductivity type selected from p-type conductivity type and n-type conductivity type; and wherein the first and second regions each comprise a second conductivity type selected from the p-type conductivity type and the n-type conductivity type, wherein the second conductivity type is different from the first conductivity type.

In at least one embodiment, the first and second states are stable states.

In another aspect of the present invention, a semiconductor memory cell comprises a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with the floating body region; and a back-bias region configured to maintain a charge in the floating body region; wherein the first region, the floating body region, and the back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of the bipolar transistor approaches unity.

In at least one embodiment, the back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and wherein the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

In at least one embodiment, the memory cell further comprises a second region in electrical contact with the floating body region and spaced apart from the first region.

In at least one embodiment, the memory cell further comprises a gate region positioned above the floating body region.

In at least one embodiment, the memory cell further comprises a substrate region, wherein the back-bias region is positioned between the substrate region and the floating body region.

In at least one embodiment, the first and second states are stable states.

In at least one embodiment, the memory cell the floating body region comprises first and second subregions, wherein the first subregion has a first doping concentration level and the second region has a second doping concentration level, and wherein the first doping concentration is different from the second doping concentration level.

In another aspect of the present invention, a semiconductor memory cell comprises a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; wherein the floating body region acts as a base region of a first bipolar transistor that maintains the state of the memory cell; and wherein the floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of the memory cell.

In at least one embodiment, the memory cell further comprises a back-bias region configured to maintain a charge in the floating body region.

In at least one embodiment, the first and second states are stable states.

In at least one embodiment, the the product of forward emitter gain and impact ionization efficiency of the first bipolar transistor approaches unity when the memory cell is in one of the first and second states, and wherein impact ionization, when the memory cell is in the other of the first and second states is less than the impact ionization when the memory cell is in the one of the first and second states.

In at least one embodiment, current flow through the first bipolar transistor is larger when the memory cell is in one of the first and second states than when the memory cell is in the other of the first and second states.

In at least one embodiment, the memory cell states are maintained through impact ionization.

In another aspect of the present invention, a semiconductor memory cell comprises: a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and a back-bias region located below the floating body region; wherein the back-bias region acts as a collector region of a bipolar transistor that maintains the state of the memory cell.

In at least one embodiment, the first and second states are stable.

In at least one embodiment, the product of forward emitter gain and impact ionization efficiency of the bipolar transistor that maintains the state of the memory cell approaches unity when the memory cell is in one of the first and second states, and wherein impact ionization, when the memory cell is in the other of the first and second states is less than the impact ionization when the memory cell is in the one of the first and second states.

In at least one embodiment, current flow through the bipolar transistor is larger when the memory cell is in one of the first and second states than when the memory cell is in the other of the first and second states.

In at least one embodiment, the memory cell states are maintained through impact ionization.

In at least one embodiment, the back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

These and other features of the invention will become apparent to those persons skilled in the art upon reading the details of the memory cells, arrays and methods as more fully described below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic, cross-sectional illustration of a memory cell according to the present invention.

FIG. 2 is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIG. 3A is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIG. 3B is a schematic, top-view illustration of the memory cell shown in FIG. 3A.

FIG. 4 schematically illustrates an equivalent circuit representation of the memory cells shown in FIGS. 1-3.

FIG. 5 schematically illustrates a bipolar device inherent in memory devices of FIGS. 1-3.

FIG. 6 schematically illustrates multiple cells of the type shown in FIGS. 1-3 joined to make a memory array.

FIG. 7 schematically illustrates a holding operation performed on a memory array according to an embodiment of the present invention.

FIG. 8 illustrates exemplary bias conditions applied on the terminals of a memory cell of the array of FIG. 7.

FIG. 9A shows an energy band diagram characterizing an intrinsic bipolar device when a floating body region is positively charged and a positive bias is applied to a buried well region of a memory cell according to an embodiment of the present invention.

FIG. 9B shows an energy band diagram of an intrinsic bipolar device when a floating body region is neutrally charged and a positive bias is applied to a buried well region of a memory cell according to an embodiment of the present invention.

FIG. 10 shows a graph of the net current I flowing into or out of a floating body region as a function of the potential V of the floating body, according to an embodiment of the present invention.

FIG. 11 shows a schematic curve of a potential energy surface (PES) of a memory cell according to an embodiment of the present invention.

FIG. 12 illustrates a charge stored in a floating body region of a memory cell as a function of a potential applied to a buried well region, connected to a BW terminal, according to an embodiment of the present invention.

FIG. 13 schematically illustrates a read operation performed on a memory array according to an embodiment of the present invention.

FIG. 14 illustrates bias conditions applied on the terminals of a memory cell to perform a read operation.

FIG. 15 schematically illustrates a write logic-0 operation performed on a memory array according to an embodiment of the present invention.

FIG. 16 illustrates bias conditions applied on the terminals of a memory cell to perform a write logic-0 operation.

FIG. 17 schematically illustrates a write logic-1 operation performed on a memory array according to an embodiment of the present invention.

FIG. 18 illustrates bias conditions applied on the terminals of a memory cell to perform a write logic-1 operation.

FIG. 19 is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIG. 20A is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIG. 20B is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIG. 21A schematically illustrates an equivalent circuit representation of the memory cells shown in FIGS. 20A-20B.

FIG. 21B schematically illustrates a bipolar device inherent in memory devices of FIGS. 20A-20B.

FIG. 22 shows an energy band diagram characterizing an intrinsic bipolar device of a memory cell according to an embodiment of the present invention under equilibrium condition.

FIG. 23 illustrates exemplary bias conditions applied on the terminals of a memory cell shown in FIGS. 20A-20B to perform a holding operation.

FIG. 24 shows an energy band diagram characterizing an intrinsic bipolar device when a floating body region is positively charged and a positive bias is applied to a buried well region of a memory cell according to an embodiment of the present invention.

FIG. 25 shows an energy band diagram of an intrinsic bipolar device when a floating body region is neutrally charged and a positive bias is applied to a buried well region of a memory cell according to an embodiment of the present invention.

FIG. 26 schematically illustrates bias conditions applied on the terminals of a memory cell to perform an alternative holding operation on a memory cell employing intrinsic silicon controlled rectifier principle according to an embodiment of the present invention.

FIG. 27 schematically illustrates bias conditions applied on the terminals of a memory cell to perform a read operation on a memory cell according to an embodiment of the present invention.

FIG. 28 schematically illustrates bias conditions applied on the terminals of a memory cell to perform a write logic-1 operation with impact ionization mechanism on a memory cell according to an embodiment of the present invention.

FIG. 29 schematically illustrates bias conditions applied on the terminals of a memory cell to perform a write logic-1 operation with band-to-band tunneling or gate induced drain leakage (GIDL) mechanism on a memory cell according to an embodiment of the present invention.

FIG. 30 schematically illustrates bias conditions applied on the terminals of a memory cell to perform a write logic-0 operation on a memory cell according to an embodiment of the present invention.

FIG. 31 schematically illustrates bias conditions applied on the terminals of a memory cell to perform a bit-selective write logic-0 operation on a memory cell according to another embodiment of the present invention.

FIG. 32A is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIG. 32B is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIG. 33 shows an energy band diagram characterizing an intrinsic bipolar device of a memory cell according to an embodiment of the present invention under equilibrium condition.

FIG. 34 is a schematic, cross-sectional illustration of an asymmetric memory cell according to another embodiment of the present invention.

FIG. 35 schematically illustrates an equivalent circuit representation of the memory cells shown in FIG. 34.

FIG. 36 schematically illustrates a bipolar device inherent in memory devices of FIG. 34.

FIG. 37 schematically illustrates a write logic-1 operation performed on a memory array according to an embodiment of the present invention.

FIG. 38 illustrates exemplary bias conditions applied on the terminals of a selected memory cell of the array of FIG. 37.

FIG. 39 illustrates exemplary bias conditions applied on the terminals of an unselected memory cell, sharing the same row as the selected cell, of the array of FIG. 37.

FIG. 40 illustrates exemplary bias conditions applied on the terminals of an unselected memory cell, sharing the same column as the selected cell, of the array of FIG. 37.

FIG. 41 illustrates exemplary bias conditions applied on the terminals of an unselected memory cell, not sharing the same row nor the same column as the selected cell, of the array of FIG. 37.

FIG. 42 schematically illustrates a write logic-0 operation performed on a memory array according to an embodiment of the present invention.

FIG. 43 illustrates exemplary bias conditions applied on the terminals of a selected memory cell of the array of FIG. 42.

FIG. 44A is a schematic, cross-sectional illustration of a memory cell which can be used as a reference cell in sensing the state of a floating body memory cell according to an embodiment of the present invention.

FIG. 44B is a schematic, cross-sectional illustration of a memory cell which can be used as a reference cell in sensing the state of a floating body memory cell according to another embodiment of the present invention.

FIG. 45A is a schematic illustration of a top view of a memory cell according to another embodiment of the present invention.

FIGS. 45B and 45C are schematic, cross-sectional illustrations of the cell of FIG. 45A taken along the I-I′ and II-II′ cut lines of FIG. 30A, respectively.

FIG. 46 schematically illustrates a memory array comprising multiple cells of the type shown in FIGS. 1-3 and a reference cell of the type shown in FIGS. 44A and 44B.

FIG. 47 schematically illustrates a memory array comprising multiple cells of the type shown in FIGS. 1-3 and a reference cell of the type shown in FIGS. 45A-45C.

DETAILED DESCRIPTION OF THE INVENTION

Before the present memory cells, arrays and methods are described, it is to be understood that this invention is not limited to particular embodiments described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims.

Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are now described. All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited.

It must be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a substrate terminal” includes a plurality of such substrate terminals and reference to “the region” includes reference to one or more regions and equivalents thereof known to those skilled in the art, and so forth.

The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided may be different from the actual publication dates which may need to be independently confirmed.

Referring to FIG. 1, a memory cell 50 according to an embodiment of the present invention is shown. Memory cell 50 includes a substrate 12 of a first conductivity type such as p-type, for example. Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, and/or other semiconductor materials. In some embodiments of the invention, substrate 12 can be the bulk material of the semiconductor wafer. In another embodiment shown in FIG. 2, substrate 12A of a first conductivity type (for example, p-type) can be a well of the first conductivity type embedded in a well 29 of the second conductivity type, such as n-type. The well 29 in turn can be another well inside substrate 12B of the first conductivity type (for example, p-type). In another embodiment, well 12A can be embedded inside the bulk of the semiconductor wafer of the second conductivity type (for example, n-type). These arrangements allow for segmentation of the substrate terminal, which is connected to region 12A. To simplify the description, the substrate 12 will usually be drawn as the semiconductor bulk material as it is in FIG. 1.

Memory cell 50 also includes a buried layer region 22 of a second conductivity type, such as n-type, for example; a floating body region 24 of the first conductivity type, such as p-type, for example; and source/drain regions 16 and 18 of the second conductivity type, such as n-type, for example.

Buried layer 22 may be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can be grown epitaxially on top of substrate 12 or formed through a solid state diffusion process.

The floating body region 24 of the first conductivity type is bounded on top by source line region 16, drain region 18, and insulating layer 62 (or by surface 14 in general), on the sides by insulating layer 26, and on the bottom by buried layer 22. Floating body 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted. Alternatively, floating body 24 may be epitaxially grown. Depending on how buried layer 22 and floating body 24 are formed, floating body 24 may have the same doping as substrate 12 in some embodiments or a different doping, if desired in other embodiments.

A source line region 16 having a second conductivity type, such as n-type, for example, is provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at surface 14. Source line region 16 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form source line region 16.

A bit line region 18, also referred to as drain region 18, having a second conductivity type, such as n-type, for example, is also provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at cell surface 14. Bit line region 18 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form bit line region 18.

A gate 60 is positioned in between the source line region 16 and the drain region 18, above the floating body region 24. The gate 60 is insulated from the floating body region 24 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Insulating layers 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 26 insulate memory cell 50 from adjacent memory cell 50. The bottom of insulating layer 26 may reside inside the buried region 22 allowing buried region 22 to be continuous as shown in FIGS. 1 and 2. Alternatively, the bottom of insulating layer 26 may reside below the buried region 22 as in FIGS. 3A and 3B (shown better in FIG. 3A). This requires a shallower insulating layer 28, which insulates the floating body region 24, but allows the buried layer 22 to be continuous in the perpendicular direction of the cross-sectional view shown in FIG. 3A. For simplicity, only memory cell 50 with continuous buried region 22 in all directions will be shown from hereon.

Cell 50 includes several terminals: word line (WL) terminal 70 electrically connected to gate 60, bit line (BL) terminal 74 electrically connected to bit line region 18, source line (SL) terminal 72 electrically connected to source line region 16, buried well (BW) terminal 76 electrically connected to buried layer 22, and substrate terminal 78 electrically connected to the substrate 12. Alternatively, the SL terminal 72 may be electrically connected to region 18 and BL terminal 74 may be electrically connected to region 16.

FIG. 4 illustrates an equivalent circuit representation of memory cell 50. Inherent in memory cell 50 are metal-oxide-semiconductor (MOS) transistor 20, formed by source line region 16, gate 60, bit line region 18, and floating body region 24, and bipolar devices 30 a and 30 b, formed by buried well region 22, floating body region 24, and source line region 16 or bit line region 18, respectively.

Also inherent in memory device 50 is bipolar device 30 c, formed by source line region 16, floating body 24, and bit line region 18. For drawings clarity, bipolar device 30 c is shown separately in FIG. 5.

FIG. 6 schematically illustrates an exemplary embodiment of a memory array 80 of memory cells 50 (four exemplary instances of memory cell 50 being labeled as 50 a, 50 b, 50 c and 50 d) arranged in rows and columns. In many, but not all, of the figures where array 80 appears, representative memory cell 50 a will be representative of a “selected” memory cell 50 when the operation being described has one (or more in some embodiments) selected memory cell(s) 50. In such figures, representative memory cell 50 b will be representative of an unselected memory cell 50 sharing the same row as selected representative memory cell 50 a, representative memory cell 50 c will be representative of an unselected memory cell 50 sharing the same column as selected representative memory cell 50 a, and representative memory cell 50 d will be representative of an unselected memory cell 50 sharing neither a row or a column with selected representative memory cell 50 a.

Present in FIG. 6 are word lines 70 a through 70 n, source lines 72 a through 72 n, bit lines 74 a through 74 p, buried well terminals 76 a through 76 n, and substrate terminal 78. Representation of the lines/terminal with letters a-n or a through p, includes not only embodiments which include literally twelve lines/terminals (i.e., a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p) or fourteen lines/terminals (i.e., a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p), but is meant to more generically represent a plurality of such line terminals, which can be less than twelve (i.e., as low as one given that there is a plurality of cells and at least one row and at least one column) or greater than twelve, thirteen or fourteen (much greater than fourteen up to any positive integer practical)).

Each of the source lines 72 a through 72 n is associated with a single row of memory cells 50 and is coupled to the source line region 18 of each memory cell 50 in that row. Each of the bit lines 74 a through 74 p is associated with a single column of memory cells 50 and is coupled to the bit line region 16 of each memory cell 50 in that column.

Substrate 12 is present at all locations under array 80. Persons of ordinary skill in the art will appreciate that one or more substrate terminals 78 may be present in one or more locations. Such skilled persons will also appreciate that although array 80 is shown in FIG. 6 as a single continuous array, many other organizations and layouts are possible. For example, word lines may be segmented or buffered, bit lines may be segmented or buffered, source lines may be segmented or buffered, the array 80 may be broken into two or more sub-arrays, control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers may be arrayed around array 80 or inserted between sub-arrays of array 80. Thus the present invention is not limited to the exemplary embodiments, features, design options, etc., shown and described.

Several operations can be performed by memory cell 50 such as holding, read, write logic-1 and write logic-0 operations, and have been described in U.S. Patent Application Publication No. 2010/00246284 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”) and U.S. Patent Application Publication No. 2010/0034041, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), which are both hereby incorporated herein, in their entireties, by reference thereto.

FIG. 7 schematically illustrates performance of a holding operation on memory array 80, while FIG. 8 shows the bias applied on the terminals of a memory cell 50 during the holding operation, according to an exemplary, non-limiting embodiment. The holding operation is performed by applying a positive back bias to the BW terminal 76, zero or negative bias on the WL terminal 70, zero bias on the BL terminal 74, SL terminal 72, and substrate terminal 78. Alternatively, the substrate terminal 78 may be left floating. In another embodiment, one of the SL terminal 72 or BL terminal 74 may be left floating. The positive back bias applied to the buried layer region 22 connected to the BW terminal 76 will maintain the state of the memory cell 50 that it is connected to. The positive bias applied to the BW terminal 76 needs to generate an electric field sufficient to trigger an impact ionization mechanism when the floating body region 24 is positively charged, as will be described through the band diagram shown in FIGS. 9A and 9B. The impact ionization rate as a function of the electric field is for example described in “Physics of Semiconductor Devices”, Sze S. M. and Ng K. K., which is hereby incorporated herein, in its entirety, by reference thereto.

In one embodiment the bias conditions for the holding operation on memory cell 50 are: 0 volts is applied to WL terminal 70, 0 volts is applied to BL terminal 74, 0 volts is applied to SL terminal 72, a positive voltage, for example, +1.2 volts is applied to BW terminal 76, and 0 volts is applied to the substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 50 and the exemplary voltages described are not limiting.

FIG. 9A shows an energy band diagram characterizing the intrinsic n-p-n bipolar device 30 b when the floating body region 24 is positively charged and a positive bias voltage is applied to the buried well region 22. The vertical dashed lines mark the different regions of the bipolar device 30 b. The energy band diagram of the intrinsic n-p-n bipolar device 30 a can be constructed in a similar manner, with the source line region 16 (connected to the SL terminal 72) in place of the bit line region 18 (connected to the BL terminal 74). The horizontal dashed lines indicate the Fermi levels in the various regions of the n-p-n transistor 30 b. The Fermi level is located in the band gap between the solid line 27 indicating the top of the valence band (the bottom of the band gap) and the solid line 29 indicating the bottom of the conduction band (the top of the band gap) as is well known in the art. If floating body 24 is positively charged, a state corresponding to logic “1” , the bipolar transistors 30 a and 30 b will be turned on as the positive charge in the floating body region lowers the energy barrier of electron flow (from the source line region 16 or bit line region 18) into the base region (floating body region 24). Once injected into the floating body region 24, the electrons will be swept into the buried well region 22 (connected to BW terminal 76) due to the positive bias applied to the buried well region 22. As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into the BW terminal 76 while the resulting hot holes will subsequently flow into the floating body region 24. When the following condition is met: β×(M−1)≈1—where β is the forward common-emitter current gain of the bipolar transistors 30 a or 30 b and M is the impact ionization coefficient—the amount of holes injected into the floating body region 24 compensates for the charge lost due to p-n junction forward bias current between the floating body region 24 and the source line region 16 or bit line region 18 and due to holes recombination. This process maintains the charge (i.e. holes) stored in the floating body region 24 which will keep the n-p-n bipolar transistors 30 a and 30 b on for as long as a positive bias is applied to the buried well region 22 through BW terminal 76.

The region where the product β×(M−1) approaches 1 and is characterized by hole current moving into the base region of a bipolar transistor is sometimes referred to as the reverse base current region and has been described for example in “A New Static Memory Cell Based on Reverse Base Current (RBC) Effect of Bipolar Transistor”, K. Sakui et al., pp. 44-47, International Electron Devices Meeting, 1988 (“Sakui-1”), “A New Static Memory Cell Based on the Reverse Base Current Effect of Bipolar Transistors”, K. Sakui et al., pp. 1215-1217, IEEE Transactions on Electron Devices, vol. 36, no. 6, June 1989 (“Sakui-2”), “On Bistable Behavior and Open-Base Breakdown of Bipolar Transistors in the Avalanche Regime—Modeling and Applications”, M. Reisch, pp. 1398-1409, IEEE Transactions on Electron Devices, vol. 39, no. 6, June 1992 (“Reisch”), which are hereby incorporated herein, in their entireties, by reference thereto.

The latching behavior based on the reverse base current region has also been described in a biristor (i.e. bi-stable resistor) for example in “Bistable resistor (Biristor)—Gateless Silicon Nanowire Memory”, J.-W. Han and Y.-K. Choi, pp. 171-172, 2010 Symposium on VLSI Technology, Digest of Technical Papers, 2010 “(“J.-W. Han”), which is hereby incorporated herein, in its entirety, by reference thereto. In a two-terminal biristor device, a refresh operation is still required. J.-W. Han describes a 200 ms data retention for the silicon nanowire biristor memory. In memory cell 50, the state of the memory cell is maintained due to the vertical bipolar transistors 30 a and 30 b, while the remaining cell operations (i.e. read and write operations) are governed by the lateral bipolar transistor 30 c and MOS transistor 20. Hence, the holding operation does not require any interruptions to the memory cell 50 access.

If floating body 24 is neutrally charged (the voltage on floating body 24 being equal to the voltage on grounded bit line region 18), a state corresponding to logic-0, no (or low) current will flow through the n-p-n bipolar devices 30 a and 30 b. The bipolar devices 30 a and 30 b will remain off and no impact ionization occurs. Consequently memory cells in the logic-0 state will remain in the logic-0 state.

FIG. 9B shows an energy band diagram of the intrinsic bipolar device 30 a when the floating body region 24 is neutrally charged and a bias voltage is applied to the buried well region 22. In this state the energy level of the band gap bounded by solid lines 27A and 29A is different in the various regions of n-p-n bipolar device 30 a. Because the potential of the floating body region 24 and the bit line region 18 is equal, the Fermi levels are constant, resulting in an energy barrier between the bit line region 18 and the floating body region 24. Solid line 23 indicates, for reference purposes, the energy barrier between the bit line region 18 and the floating body region 24. The energy barrier prevents electron flow from the bit line region 18 (connected to BL terminal 74) to the floating body region 24. Thus the n-p-n bipolar device 30 a and 30 b will remain off.

Sakui-1 and Sakui-2 describe a memory cell based on the reverse base current effect, where the base of a n-p-n bipolar transistor is connected to a p-type MOS transistor. Reisch describes the challenges with the memory cell described in Sakui-1 and Sakui-2, which includes the requirement for the current of the p-type MOS transistor. Because the collector terminal of the bipolar transistor also serves as the channel of the p-type MOS transistor, any changes in operating conditions or process conditions will affect both the bipolar transistor and the p-type MOS transistor. For example, increasing the doping level of the collector region will improve the impact ionization efficiency. However, it will also increase the doping level of the p-type MOS transistor channel region, and reduces the drive current of the p-type MOS transistor.

An autonomous refresh for a floating body memory, without requiring to first read the memory cell state, has been described for example in “Autonomous Refresh of Floating Body Cell (FBC)”, Ohsawa et al., pp. 801-804, International Electron Device Meeting, 2008 (“Ohsawa”), U.S. Pat. No. 7,170,807 “Data Storage Device and Refreshing Method for Use with Such Device”, Fazan et al. (“Fazan”), which are hereby incorporated herein, in their entireties, by reference thereto. Ohsawa and Fazan teach an autonomous refresh method by applying a periodic gate and drain voltage pulses, which interrupts access to the memory cells being refreshed. In memory cell 50, more than one stable state is achieved because of the vertical bipolar transistors 30 a and 30 b. The read and write operations of the memory cell 50 are governed by the lateral bipolar transistor 30 c and MOS transistor 20. Hence, the holding operation does not require any interruptions to the memory cell 50 access.

In the holding operation described with regard to FIG. 7, there is no individually selected memory cell. Rather the holding operation will be performed at all cells connected to the same buried well terminal 76. In addition, the holding operation does not interrupt read or write access to the memory cell 50.

FIG. 10 shows a graph of the net current I flowing into or out of the floating body region 24 as a function of the potential V of the floating body 24 (not drawn to scale). A negative current indicates a net current flowing into the floating body region 24, while a positive current indicates a net current flowing out of the floating body region 24. At low floating body 24 potential, between 0V and V_(FB0) indicated in FIG. 10, the net current is flowing into the floating body region 24 as a result of the p-n diode formed by the floating body region 24 and the buried well region 22 being reverse biased. If the value of the floating body 24 potential is between V_(FB0) and V_(TS), the current will switch direction, resulting in a net current flowing out of the floating body region 24. This is because of the p-n diode, formed by the floating body region 24 and the buried well region 22, being forward biased as the floating body region 24 becomes increasingly more positive. As a result, if the potential of the floating body region 24 is less than V_(TS), then at steady state the floating body region 24 will reach V_(FB0). If the potential of the floating body region 24 is higher than V_(TS), the current will switch direction, resulting in a net current flowing into the floating body region 24. This is as a result of the base current flowing into the floating body region 24 being greater than the p-n diode leakage current. When the floating body 24 potential is higher than V_(FB1), the net current will be out of the floating body region 24. This is because the p-n diode leakage current is once again greater than the base current of the bipolar devices 30 a and 30 b.

The holding operation results in the floating body memory cell having two stable states: the logic-0 state and the logic-1 state separated by an energy barrier, which are represented by V_(FB0), V_(FB1), and V_(TS), respectively. FIG. 11 shows a schematic curve of a potential energy surface (PES) of the memory cell 50, which shows another representation of the two stable states resulting from applying a back bias to the BW terminal 76 (connected to the buried well region 22).

The values of the floating body 24 potential where the current changes direction, i.e. V_(FB0), V_(FB1), and Y_(TS), can be modulated by the potential applied to the BW terminal 76. These values are also temperature dependent.

The holding/standby operation also results in a larger memory window by increasing the amount of charge that can be stored in the floating body 24. Without the holding/standby operation, the maximum potential that can be stored in the floating body 24 is limited to the flat band voltage V_(FB) as the junction leakage current to regions 16 and 18 increases exponentially at floating body potential greater than V_(FB). However, by applying a positive voltage to substrate terminal 78, the bipolar action results in a hole current flowing into the floating body 24, compensating for the junction leakage current between floating body 24 and regions 16 and 18. As a result, the maximum charge V_(MC) stored in floating body 24 can be increased by applying a positive bias to the substrate terminal 78 as shown in FIG. 12. The increase in the maximum charge stored in the floating body 24 results in a larger memory window.

Floating body DRAM cells described in Ranica-1, Ranica-2, Villaret, and Pulicani only exhibit one stable state, which is often assigned as logic-0 state. Villaret describes the intrinsic bipolar transistors enhance the data retention of logic-1 state, by drawing the electrons which otherwise would recombine with the holes stored in the floating body region. However, only one stable state is observed because there is no hole injection into the floating body region to compensate for the charge leakage and recombination.

The operation range to satisfy the holding operation condition β×(M−1)≈1 is low β and high M to high β and low M. The low β, high M condition is preferred as it results in a lower power for the holding operation since the current flow (from the collector (BW terminal 76) to the emitter (source line region 16 or bit line region 18) is proportional to β. Therefore, the lower the common-emitter gain β (i.e. the closer β is to 1), the lower the current consumed during the holding operation is (a common value of β would be between 20 and 500). Process conditions that result in low β, high M will be described below, following discussion on the read and write operations.

The read and write operations of the memory cell have been described, for example, in Widjaja-1 and Widjaja-2. An active low read scheme—where the selected BL terminal 74 is biased at low voltage, for example, at zero voltage—will be described in FIGS. 13 and 14, where the following bias conditions are applied: a positive voltage is applied to the BW terminal 76 a, a positive voltage is applied to the selected SL terminal 72 a, zero voltage is applied to the selected BL terminal 74 a, a positive voltage applied to the selected WL terminal 70 a, while zero voltage is applied to the substrate terminal 78 a. The positive voltage applied to SL terminal 72 may be less than the positive voltage applied to WL terminal 70, in which the difference in the threshold voltage of the memory cell 50 is employed to represent the state of the memory cell 50. The positive voltage applied to SL terminal 72 may also be greater than or equal to the positive voltage applied to WL terminal 70 and may generate sufficiently high electric field to trigger the bipolar read mechanism When cell 50 is in an array 80 of cells 50, the unselected BL terminals 74 (e.g., 74 b, . . . 74 n) will be biased at the same voltage applied to the selected SL terminal, the unselected SL terminals 72 will be at zero voltage, and the unselected WL terminals 70 (e.g., 70 n and any other WL terminals 70 not connected to selected cell 50 a) will remain at zero or negative voltage.

In one particular non-limiting embodiment, about 0.0 volts is applied to the selected BL terminal 74 a, about +0.4 volts is applied to the selected SL terminal 72 a, about +1.2 volts is applied to the selected WL terminal 70 a, about +1.2 volts is applied to BW terminal 76, and about 0.0 volts is applied to terminal 78, as illustrated in FIG. 13. The unselected SL terminals 72 remain at 0.0 volts, the unselected BL terminals 74 are biased at +0.4 volts, and the unselected WL terminals 70 remain at 0.0 volts as illustrated in FIG. 13. However, these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above.

A row write logic-0 operation is described in FIGS. 15 and 16, where the following bias conditions are applied: a negative voltage is applied to the selected SL terminal 72 a, zero or positive voltage is applied to the BW terminal 76, zero voltage or negative voltage is applied to the WL terminal 70, and zero voltage is applied to BL terminal 74 and substrate terminal 78; while zero voltage is applied to the unselected SL terminals 72. Under these conditions, the p-n junction between floating body 24 and source line region 16 of the selected cell 50 is forward-biased, evacuating holes from the floating body 24. All memory cells 50 sharing the same SL terminal 72 a will be written to simultaneously. To write arbitrary binary data to different memory cells 50, a write logic-0 operation is first performed on all the memory cells to be written, followed by one or more write logic-1 operations on the memory cells that must be written to logic-1.

In one particular non-limiting embodiment, about −1.2 volts is applied to selected SL terminal 72 a, about 0.0 volts is applied to WL terminal 70 a, about 0.0 volts or +1.2 volts is applied to BW terminal 76 a, and about 0.0 volts is applied to substrate terminal 78 a. These voltage levels are exemplary only may vary from embodiment to embodiment.

A write logic-0 operation may also be performed by applying the following bias conditions: a negative voltage to the selected BW terminal 76, zero voltage is applied to the WL terminal 70, SL terminal 72, BL terminal 74, and substrate terminal 78. Under these conditions, the p-n junction between floating body 24 and buried well 22 of the selected cell 50 is forward-biased, evacuating any holes from the floating body 24. In one particular non-limiting embodiment, about −0.5 volts is applied to BW terminal 76, about 0.0 volts is applied to WL terminal 70, SL terminal 72, BL terminal 76, and substrate terminal 78. A lower negative voltage may also be applied to the substrate terminal 78 to prevent the p-n diode formed between the substrate terminal 78 and the BW terminal 76 to be forward biased.

An active low write logic-1 operation is shown in FIGS. 17 and 18, where the following bias conditions are applied: a positive voltage is applied to the BW terminal 76 a, a positive voltage is applied to the selected SL terminal 72 a, zero voltage is applied to the selected BL terminal 74 a, a positive voltage applied to the selected WL terminal 70 a, while zero voltage is applied to the substrate terminal 78 a. The positive voltage applied to the selected SL terminal 72 a is greater than or equal to the positive voltage applied to the selected WL terminal 70 a and may generate sufficiently high enough electric field to trigger impact ionization mechanism. The impact ionization rate as a function of the electric field is for example described in “Physics of Semiconductor Devices”, Sze S. M. and Ng K. K., which is hereby incorporated herein, in its entirety, by reference thereto.

When cell 50 is in an array 80 of cells 50, the unselected BL terminals 74 (e.g., 74 b, 74 n) will be biased at the same voltage applied to the selected

SL terminal, the unselected SL terminals 72 will be at zero voltage, and the unselected WL terminals 70 (e.g., 70 n and any other WL terminals 70 not connected to selected cell 50 a) will remain at zero or negative voltage. A negative voltage can be applied on the unselected WL terminals 70 to suppress the electron flow from the bit line region 18 to source line region 16, thus reducing the probability that unselected cells in logic-0 state will be accidentally written to logic-1. (The negative voltage will also reduce the probability of undesired write, often referred to as write disturb, in active high write logic-1 scheme).

In one particular non-limiting embodiment, about 0.0 volts is applied to the selected BL terminal 74 a, about +1.2 volts is applied to the selected SL terminal 72 a, about +1.2 volts is applied to the selected WL terminal 70 a, about +1.2 volts is applied to BW terminal 76, and about 0.0 volts is applied to terminal 78 a, as illustrated in FIG. 17. The unselected SL terminals 72 remain at 0.0 volts, the unselected BL terminals 74 are biased at +1.2 volts, and the unselected WL terminals 70 remain at 0.0 volts as illustrated in FIG. 17. However, these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above.

Low β and high impact ionization efficiency M will result in a more efficient holding operation. In an embodiment of the memory cell 50G shown in FIG. 19, the buried well region 22G comprises a material with a low band gap (relative to the band gap of silicon, which is about 1.12 eV) , examples of which include germanium (band gap is ˜0.7 eV) and silicon germanium (band gap depends on the ratio of silicon and germanium), which band gap is lower than that of silicon (band gap is ˜1.12 eV). The lower band gap results in a lower energy necessary to create an electron-hole pair, thus increases the impact ionization efficiency M. The lower band gap also results in a lower voltage that can be applied to the BW terminal 76 during the operation of the memory cell 50G. For example, using germanium as the buried well region 22G may result in a holding voltage as low as 0.7V to be applied to the BW terminal 76. A lower band gap can also be obtained by having the buried well region 22G heavily doped. For example, H. P. D Lanyon and R. A. Tuft describe the band gap narrowing in silicon in “Bandgap Narrowing in Moderately to Heavily Doped Silicon”, pp. 1014-1018, IEEE Transactions on Electron Devices, vol. ED-26, no. 7, July 1979. The lower band gap region 22G can be formed through ion implantation process, solid state diffusion, and/or through epitaxial growth process.

In another embodiment of the memory cell 150 shown in FIG. 20A, the floating body region 24 may comprise regions having different doping concentrations having the same conductivity type. FIG. 20A illustrates an example of floating body region 24 comprising three different regions 24 a, 24 b, and 24 c. Region 24 a, which is the closest one to the surface region 14, may have the lowest doping concentration to reduce the random dopant fluctuation (RDF) and hence improve the variability of the memory cell performance, for example its threshold voltage. The doping concentration of region 24 b may be, but not necessarily, lower than the doping concentration of region 24 c, but higher than that of region 24 a. Region 24 b may also function as a barrier layer to suppress dopant diffusion, for example but not limited to Si:C layer. This prevents dopant diffusion from the heavier doped region 24 c to the lowest doped region 24 a. The different floating body regions 24 a, 24 b, and 24 c, may be formed through ion implantation process, solid-state diffusion, and/or epitaxial growth.

FIG. 20B illustrates another example of another embodiment of memory cell 150 according to the present invention, where regions 24 b and 24 c are localized, for example between the regions 16 and 18, meaning that regions 24 b and 24 c do not underlie all portions of regions 16 and 18. The remainder of region 24 outside of regions 24 b and 24 c underlies all portions of regions 16 and 18 and is considered to be region 24 a in this embodiment.

FIG. 21A illustrates an equivalent circuit representation of memory cell 150. Inherent in memory cell 150 are metal-oxide-semiconductor (MOS) transistor 120, formed by source line region 16, gate 60, bit line region 18, and floating body region 24, and bipolar devices 130 a and 130 b, formed by buried well region 22, floating body region 24, and source line region 16 or bit line region 18, respectively.

Also inherent in memory device 150 is bipolar device 130 c, formed by source line region 16, floating body 24, and bit line region 18. For drawings clarity, bipolar device 30 c is shown separately in FIG. 21B.

FIG. 22 illustrates an energy band diagram characterizing the intrinsic n-p-n bipolar device 130 a formed by the source line region 16, floating body region 24, and the buried well region 22 when the n-p-n bipolar device is in equilibrium for the memory cell 150 comprising of regions with different doping concentrations 24 a, 24 b, and 24 c. The vertical dashed lines mark the regions with different doping concentrations of the bipolar device 130 b. The energy band diagram of the intrinsic n-p-n bipolar device 130 b can be constructed in a similar manner, with the bit line region 18 (connected to the BL terminal 74) in place of the source line region 16 (connected to the SL terminal 72). The dashed horizontal lines indicate the Fermi levels in the various regions of the n-p-n bipolar device 130 a. The Fermi level is located in the band gap between the solid line 27 indicating the top of the valence band (the bottom of the band gap) and the solid line 29 indicating the bottom of the conduction band (the top of the band gap) as is well known in the art. The different regions of the floating body 24 are indicated in FIG. 22. Because of the different doping concentration in different regions of floating body 24, the Fermi level is also different across different regions. In the band diagram illustrated in FIG. 22, region 24 c with the highest doping concentration has the lowest energy for holes storage. As a result, when memory cell 150 stores holes in the floating body region 24, holes storage will be concentrated in region 24 c.

FIG. 23 schematically illustrates performance of a holding operation on memory cell 150 comprising different regions of floating body 24. The holding operation is similar to that of memory cell 50 shown in FIGS. 7 and 8 and is performed by applying a positive back bias to the BW terminal 76, zero bias on the WL terminal 70, BL terminal 74, SL terminal 72, and substrate terminal 78. The positive back bias applied to the buried layer region 22 connected to the BW terminal 76 will maintain the state of the memory cell 50 that it is connected to. The positive bias applied to the BW terminal 76 needs to generate sufficient electric field to trigger impact ionization mechanism as will be described through the band diagram shown in FIGS. 24 and 25. The impact ionization rate as a function of the electric field is for example described in “Physics of Semiconductor Devices”, Sze S. M. and Ng K. K., which is hereby incorporated herein, in its entirety, by reference thereto.

In one embodiment the bias conditions for the holding operation on memory cell 150 is: 0 volts is applied to WL terminal 70, 0 volts is applied to BL terminal 74, 0 volts is applied to SL terminal 72, a positive voltage, for example, +1.2 volts is applied to BW terminal 76, and 0 volts is applied to the substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 150 and the exemplary voltages described are not limiting.

FIG. 24 shows an energy band diagram characterizing the intrinsic n-p-n bipolar device 130 a when the floating body region 24 is positively charged and a positive bias voltage is applied to the buried well region 22. The energy band diagram of the intrinsic n-p-n bipolar device 130 b can be constructed in a similar manner, with the bit line region 18 (connected to the BL terminal 74) in place of the bit line region 16 (connected to the SL terminal 72). If floating body 24 is positively charged, a state corresponding to logic-1, the bipolar transistors 130 a and 130 b will be turned on as the positive charge in the floating body region lowers the energy barrier of electron flow into the base region. Once injected into the floating body region 24, the electrons will be swept into the buried well region 22 (connected to BW terminal 76) due to the positive bias applied to the buried well region 22. As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into the BW terminal 76 while the resulting hot holes will subsequently flow into the floating body region 24. This process restores the charge on floating body 24 and will maintain the charge stored in the floating body region 24 which will keep the n-p-n bipolar transistors 130 a and 130 b on for as long as a positive bias is applied to the buried well region 22 through BW terminal 76.

The higher doping concentration of region 24 c relative to the remaining floating body regions 24 a and 24 b result in a higher electric field between the floating body region 24 c and the buried well region 22. This results in a more efficient impact ionization mechanism, which in turn results in a lower voltage applied to the buried well region needed for the holding operation.

If floating body 24 is neutrally charged (the voltage on floating body 24 being equal to the voltage on grounded source line region 16), a state corresponding to logic-0, no current will flow through the n-p-n bipolar devices 130 a and 130 b. The bipolar devices 130 a and 130 b will remain off and no impact ionization occurs. Consequently memory cells in the logic-0 state will remain in the logic-0 state.

FIG. 25 shows an energy band diagram of the intrinsic bipolar device 130 a when the floating body region 24 is neutrally charged and a bias voltage is applied to the buried well region 22. In this state the energy level of the band gap bounded by solid lines 27A and 29A is different in the various regions of n-p-n bipolar device 130a. Because the potential of the floating body region 24 and the source line region 16 is equal, the Fermi levels are constant, resulting in an energy barrier between the source line region 16 and the floating body region 24. Solid line 23 indicates, for reference purposes, the energy barrier between the source line region 16 and the floating body region 24. The energy barrier prevents electron flow from the source line region 16 (connected to BL terminal 72) to the floating body region 24. Thus the n-p-n bipolar devices 130 a and 130 b will remain off.

In the holding operation described with regard to FIG. 23, there is no individually selected memory cell. Rather the holding operation will be performed at all cells connected to the same buried well terminal 76.

An alternative holding operation employing the intrinsic silicon controlled rectifier (SCR) device of memory cell, as described for example in Widjaja-2, may also be performed on memory cell 150. FIG. 26 illustrates bias conditions for an alternative holding operation applied on memory cell 150, as described for example in U.S. Pat. No. 8,077,536, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle”, which is incorporated by reference herein in its entirety. The holding operation may also be performed by applying the following bias conditions: zero voltage is applied to WL terminal 70, SL terminal 72, and BL terminal 74, a positive voltage is applied to the substrate terminal 78, while the BW terminal 76 is left floating. Under these conditions, if memory cell 150 is in memory/data state “1” with positive voltage in floating body 24, the intrinsic silicon controlled rectifier (SCR) device of memory cell 150, formed by the substrate 12, the buried well region 22, the floating body region 24, and the bit line region 16 or the source line region 18, is turned on, thereby maintaining the state “1” data. Memory cells in state “0” will remain in blocking mode, since the voltage in floating body 24 is not substantially positive and therefore floating body 24 does not turn on the SCR device. Accordingly, current does not flow through the SCR device and these cells maintain the state “0” data. In this way, an array of memory cells 150 may be refreshed by periodically applying a positive voltage pulse through substrate terminal 78. Those memory cells 150 that are commonly connected to substrate terminal 78 and which have a positive voltage in body region 24 will be refreshed with a “1” data state, while those memory cells 150 that are commonly connected to the substrate terminal 78 and which do not have a positive voltage in body region 24 will remain in blocking mode, since their SCR device will not be turned on, and therefore memory state “0” will be maintained in those cells. In this way, all memory cells 150 commonly connected to the substrate terminal will be maintained/refreshed to accurately hold their data states. This process occurs automatically, upon application of voltage to the substrate terminal 78, in a parallel, non-algorithmic, efficient process. In one particular non-limiting embodiment, a voltage of about 0.0 volts is applied to BL terminal 74, a voltage of about 0.0 volts is applied to WL terminal 70, about 0.0 volts is applied to SL terminal 72, and about +1.2 volts is applied to terminal 78, while the BW terminal 76 is left floating. However, these voltage levels may vary, while maintaining the relative relationships therebetween.

The amount of charge stored in the floating body 24 can be sensed by monitoring the cell current of the memory cell 150. If the memory cell is in a logic-1 state having holes in the floating body region 24, then the memory cell 150 will have a lower threshold voltage (gate voltage where the transistor is turned on), and consequently a higher cell current, compared to when the floating body memory cell 150 is in logic-0 state having no holes in the floating body region 24. The higher doping concentration of region 24 c will also result in a larger difference between the logic-0 and logic-1 states.

FIG. 27 illustrates an exemplary bias condition applied to the memory cell 150 for performing a read operation. The read operation is performed by applying the following bias conditions: a positive bias to the WL terminal 70, a positive bias to the BL terminal 74, zero bias to the SL terminal 72, zero or positive bias to the BW terminal 76, and zero bias to the substrate terminal 78.

In one embodiment the bias conditions for the read operation for memory cell 150 are: +1.2 volts is applied to WL terminal 70, +0.4 volts is applied to BL terminal 74, 0.0 volts is applied to SL terminal 72, +1.2 volts is applied to BW terminal 76, and 0.0 volts is applied to the substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 150 and the exemplary voltages described are not limiting. The positive voltage applied to BL terminal 74 may be less than the positive voltage applied to WL terminal 70, in which the difference in the threshold voltage of the memory cell 150 is employed to represent the state of the memory cell 150. The positive voltage applied to BL terminal 74 may also be greater than or equal to the positive voltage applied to WL terminal 70 and may generate sufficiently high electric field to trigger the bipolar read mechanism.

A sensing circuit typically connected to BL terminal 74 can be used to determine the data state of the memory cell 150. Any sensing scheme known in the art can be used in conjunction with memory cell 150.

A higher doping concentration of region 24 c also results in a higher body effect, which in turn results in a greater difference between the characteristics of memory cells in logic-0 and logic-1 states.

FIG. 28 illustrates exemplary bias conditions for an active high write logic-1 operation on the memory cell 150, where the following bias conditions are applied: a positive voltage is applied to the selected WL terminal 70, a positive voltage is applied to the selected BL terminal 74, zero voltage is applied to the selected SL terminal 72, zero or positive voltage is applied to the selected BW terminal 76, and zero voltage is applied to the substrate terminal 78. This positive voltage applied to the selected BL terminal 74 is greater than or equal to the positive voltage applied to the selected WL terminal 70 and may generate sufficiently high enough electric field to trigger impact ionization mechanism.

In one particular non-limiting embodiment, about +1.2 volts is applied to the selected WL terminal 70, about +1.2 volts is applied to the selected BL terminal 74, about 0.0 volts is applied to SL terminal 72, about 0.0 volts or +1.2 volts is applied to BW terminal 76, and about 0.0 volts is applied to substrate terminal 78; while about 0.0 volts is applied to the unselected WL terminals 70, unselected BL terminals 74, unselected SL terminals, and substrate terminal 78, and 0.0 volts or +1.2 volts is applied to BW terminal 76. These voltage levels are exemplary only and may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.

In another example, the positive voltage applied to the selected WL terminal 70 is about one-half of the positive voltage applied to the selected BL terminal 74. These bias conditions result in a high impact ionization efficiency, which will shorten the excess hole charging time to the floating body region 24 and consequently increase the speed for the write logic-1. In addition, the power required for the write logic-1 operation can be reduced since a lower gate voltage results in a lower current flow (from the BL terminal 74 to the SL terminal 72) compared to the current flow when the voltage applied to the selected WL terminal 70 is equal to the positive voltage applied to the selected BL terminal 74.

In another particular non-limiting embodiment, about +0.6 volts is applied to the selected WL terminal 70, about +1.2 volts is applied to the selected BL terminal 74, about 0.0 volts is applied to SL terminal 72, about 0.0 volts or +1.2 volts is applied to BW terminal 76, and about 0.0 volts is applied to substrate terminal 78; while about 0.0 volts is applied to the unselected WL terminals 70, unselected BL terminals 74, unselected SL terminals, and substrate terminal 78, and 0.0 volts or +1.2 volts is applied to BW terminal 76. These voltage levels are exemplary only and may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.

In another embodiment of the memory cell 150, the doping concentration of region 24 b may be lower than the doping concentration of region 24 a and lower than the doping concentration of region 24 c (while the doping concentration of region 24 c is higher than that of region 24 a). This results in a current flow in the region 24 b, away from the surface 14 of the memory cell 150. This will be advantageous for logic-1 write operation using impact ionization mechanism, as the hot electron will be generated away from the surface 14, hence reduces the damage of gate oxide 62 due to hot electron effect and improves the reliability of the memory cell 150.

FIG. 29 is a schematic illustration showing bias conditions for a write logic-1 operation using band-to-band tunneling mechanism performed on memory cell 150, where the following bias conditions are applied: a negative voltage is applied to the selected WL terminal 70, a positive voltage is applied to the selected BL terminal 74, zero voltage is applied to the selected SL terminal 72, zero or positive voltage is applied to the selected BW terminal 76, and zero voltage is applied to the substrate terminal 78.

In one particular non-limiting embodiment, about −1.2 volts is applied to the selected WL terminal 70, about +1.2 volts is applied to the selected BL terminal 74, about 0.0 volts is applied to SL terminal 72, about 0.0 volts or +1.2 volts is applied to BW terminal 76, and about 0.0 volts is applied to substrate terminal 78; while about 0.0 volts is applied to the unselected WL terminals 70, unselected BL terminals 74, unselected SL terminals, and substrate terminal 78, and 0.0 volts or +1.2 volts is applied to BW terminal 76. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.

The negative charge on the gate 60 (connected to WL terminal 70) and the positive voltage on bit line region 18 (connected to BL terminal 74) create a strong electric field (for example, about 10⁶ V/cm in silicon, as described in Sze, p. 104) between the bit line region 18 and the floating body region 24 in the proximity of gate 60. This bends the energy band sharply upward near the gate and bit line junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current, while the holes are injected into floating body region 24 and become the hole charge that creates the logic-1 state.

FIG. 30 is a schematic illustration showing bias conditions for a write logic-0 operation which can be performed by applying a negative voltage bias to the selected SL terminal 72, zero bias to the selected WL terminal 70, zero bias to the BL terminal 74, zero or positive bias to the BW terminal 76, and zero bias to the substrate terminal 78; while zero voltage is applied to the unselected SL terminals 72, zero voltage bias applied to the unselected WL terminals 70, zero or positive bias applied to the BW terminal 76, and zero voltage bias applied to the substrate 78. Under these conditions, the p-n junction between floating body 24 and source line region 16 of the selected cell 150 is forward-biased, evacuating holes from the floating body 24. All memory cells 150 sharing the same selected SL terminal 72 a will be written to simultaneously. To write arbitrary binary data to different memory cells 150, a write logic-0 operation is first performed on all the memory cells to be written, followed by one or more write logic-1 operations on the memory cells that must be written to logic-1.

In one particular non-limiting embodiment, about −1.2 volts is applied to selected SL terminal 72, about 0.0 volts is applied to WL terminal 70, about 0.0 volts is applied to BL terminal 74, about 0.0 volts or +1.2 volts is applied to BW terminal 76, and about 0.0 volts is applied to substrate terminal 78, while zero voltage is applied to the unselected SL terminals 72, zero voltage bias applied to the unselected WL terminals 70, zero or positive bias applied to the BW terminal 76, and zero voltage bias applied to the substrate 78. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.

FIG. 31 illustrates a bit-selective write logic-0 operation performed on a selected memory cell 150, where the following bias conditions are applied: a positive voltage to the selected WL terminal 70, a negative voltage to the selected BL terminal 74, zero voltage bias to the selected SL terminal 72, zero or positive voltage bias to the BW terminal 76, and zero voltage to the substrate terminal 78; while zero voltage is applied to the unselected WL terminals 70, zero voltage is applied to the unselected BL terminals 74, zero voltage bias is applied to the unselected SL terminals 72, zero or positive voltage is applied to the BW terminal 76, and zero voltage is applied to the substrate terminal 78. Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70. As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74, the p-n junction between floating body region 24 and bit line region 18 is forward-biased, evacuating holes from the floating body 24.

To reduce undesired write logic-0 disturb to other memory cells 150 in a memory array, the applied potential can be optimized as follows: if the floating body 24 potential of state logic-1 is referred to as V_(FB1), then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by V_(FB1)/2 while −V_(FB1)/2 is applied to BL terminal 74. Additionally, either ground or a slightly positive voltage may also be applied to the BL terminals 74 of unselected memory cells 150 that do not share the same BL terminal 74 as the selected memory cell 150, while a negative voltage may also be applied to the WL terminals 70 of unselected memory cells 150 that do not share the same WL terminal 70 a as the selected memory cell 150.

As illustrated in FIG. 31, the following exemplary bias conditions may be applied to the selected memory cell 50 to perform a bit-selective write logic-0 operation: a potential of about −0.2 volts to the selected BL terminal 74, a potential of about +1.2 volts to the selected WL terminal 70, about 0.0 volts is applied to the selected SL terminal 72, a potential of about 0.0 volts or +1.2 volts to the BW terminal 76, about 0.0 volts to the substrate terminal 78.

FIG. 32A illustrates memory cell 250 according to another embodiment of the present invention, which comprises halo regions 17 and 19 of the first conductivity type respectively adjacent to the source line region 16 and bit line region 18 of the second conductivity type. Memory cell 250 may comprise both halo regions 17 and 19, or memory cell 250 may comprise only one halo region 17 or 19, as shown in an asymmetric cell 250 in FIG. 32B. FIG. 32A also shows floating body region 24 comprises, although not necessarily, different doping concentrations 24 a, 24 b, and 24 c. The halo regions 17 or 19 can be located at an angle with respect to the surface 14, such as shown in FIG. 32A or could be located below the source line region 16 or bit line region 18, such as shown in FIG. 32B.

FIG. 33 illustrates the band diagram of memory cell 250 under equilibrium condition. Because of the different doping concentrations, multiple regions with lower energy for holes exist in memory cell 250. For example, regions of low energy for holes storage are available in halo region 17 (and 19) and region 24 c. Multiple storage locations can be used to construct a multi-level cell with a memory cell 250 storing holes in different regions of the memory cell 250.

FIG. 34 illustrates a cross-sectional view of another embodiment of the memory cell 350. Memory cell 350 is asymmetric in that the source line region 16 and the bit line region 18 have different physical properties, for example the junction depth, and electrical properties, for example the breakdown voltage. As will be described, asymmetric memory cell 350 has some advantages, for example, allowing for a write logic-1 operation through impact ionization mechanism away from the surface region 14. This results in less degradation of the gate oxide 62. The source line region 16 (connected to the SL terminal 72) is shown to have a deeper junction depth in FIG. 34 than that of bit line region 18. In another embodiment of the memory cell 350, the bit line region 18 may have a deeper junction depth than the source line region 16.

An equivalent circuit representation of memory cell 350 is shown in FIG. 35. The vertical bipolar device 330 a—formed by the source line region 16, floating body region 24, and buried well region 22—is schematically shown to be larger in size compared to the vertical bipolar device 330 b, formed by the bit line region 18, floating body region 24, and buried well region 22. For the same bias conditions (for example the same voltage difference across the emitter and collector terminals, i.e. the buried well region 22 and the source line region 16 or the bit line region 18), the vertical bipolar device 330 a will conduct a higher current because of the narrower base region of the bipolar device 330 a. Similarly, the emitter-collector breakdown voltage, which results in impact ionization at the collector region (buried well region 22) and subsequently injects holes into the floating body region 24, is lower for bipolar device 330 a compared to that of bipolar device 330 b.

Also inherent in memory device 350 is bipolar device 330 c, formed by source line region 16, floating body 24, and bit line region 18. For drawings clarity, bipolar device 330 c is shown separately in FIG. 36.

The operations performed on the memory cell 350 are similar to those of memory cell 50. Due to the asymmetric nature of the memory cell 350, further optimizations can be performed to the write operations.

FIG. 37 schematically illustrates a write logic-1 operation performed on memory array 380, where the following bias conditions are applied to the selected memory cell 350 a: a positive voltage is applied to the selected WL terminal 70, zero voltage is applied to the selected BL terminal 74, a positive voltage is applied to the BW terminal 76, zero voltage is applied to the substrate terminal 78, and selected SL terminal 72 is left floating; while the following bias conditions are applied to the unselected terminals: zero voltage is applied to the unselected WL terminal 70, a positive voltage is applied to the unselected BL terminal 74, a positive voltage is applied to the unselected SL terminal 72, a positive voltage is applied to the unselected BW terminal, and zero voltage is applied to the unselected substrate terminal 78 (in the case of memory array 380 where the BW terminals 76 and substrate terminals 78 are segmented).

In one particular non-limiting embodiment, about +0.6 volts is applied to selected WL terminal 70, about 0.0 volts is applied to the selected BL terminal 74, about +1.2 volts is applied to the selected BW terminal 76, about 0.0 volts is applied to the substrate terminal 78, while selected SL terminal 72 is left floating; while about 0.0 volts is applied to the unselected WL terminal 70, about +0.6 volts is applied to the unselected BL terminal 74, and about +0.6 volts is applied to the unselected SL terminal 72. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.

The bias conditions on the selected memory cell 350 a are shown in FIG. 38. The positive voltage applied to the selected WL terminal 70 a will turn on the MOS transistor 320 and pull the source line region 16 (which is floating) to about zero voltage (the potential applied to the BL terminal 74 a). Because the bipolar transistor 330 a has a lower emitter-collector breakdown voltage, this will result in electron flow from the source line region 16 to the buried well region 22. The electron flow will result in impact ionization at the interface of the buried well region 22 and the floating body region 24, and hot holes will be injected to the floating body region 24. No (or significantly lower) electron flow will occur through the bipolar transistor 330 b as it has a higher emitter-collector breakdown voltage.

FIG. 39 shows the bias conditions on the unselected memory cell 350 b, which is a representative of an unselected memory cell in the same row as the selected memory cell 350 a. The potential of the floating source line region 16 for the memory cell 350 b will be about the voltage difference between the gate voltage and the threshold voltage of the MOS transistor 320. The emitter-collector voltage (the difference between the potential of the buried well region 22 and the source line region 16 or the bit line region 18) is lower than the emitter-collector breakdown voltage of both bipolar transistors 330 a and 330 b and thus no (or significantly lower) impact ionization occurs on the unselected memory cell 350 b.

FIG. 40 shows the bias conditions on the unselected memory cell 350 c, which is a representative of an unselected memory cell sharing the same column as the selected memory cell 350 a. The emitter-collector voltages of the bipolar transistor 330 a and 330 b are both lower than the emitter-collector breakdown voltages of both bipolar transistor 330 a and 330 b and thus no (or significantly lower) impact ionization occurs on the unselected memory cell 350 c.

FIG. 41 shows the bias conditions on the unselected memory cell 350 d, which is a representative of an unselected memory cell sharing neither row nor column with the selected memory cell 350 a. The emitter-collector voltages of the bipolar transistor 330 a and 330 b are both lower than the emitter-collector breakdown voltages of both bipolar transistor 330 a and 330 b and thus no (or significantly lower) impact ionization occurs on the unselected memory cell 350 d.

A write logic-0 is performed on the memory cell 350 as shown in FIGS. 42 and 43 through the application of the following bias conditions: a negative voltage is applied to the selected SL terminal 72, zero or negative voltage is applied to the selected WL terminal 70, zero voltage is applied to the BL terminal 74, zero or positive voltage is applied to the selected BW terminal 76, and zero voltage is applied to the selected substrate terminal 78; while zero voltage is applied to the unselected SL terminal 72, BL terminal 74, and substrate terminal 78, zero or negative voltage is applied to the unselected WL terminal 70, and zero or positive voltage is applied to the selected BW terminal 76.

Under these conditions, the p-n junction between floating body 24 and source line region 16 of the selected cell 350 is forward-biased, evacuating holes from the floating body 24. All memory cells 350 sharing the same selected SL terminal 72 a will be written to simultaneously. To write arbitrary binary data to different memory cells 350, a write logic-0 operation is first performed on all the memory cells to be written, followed by one or more write logic-1 operations on the memory cells that must be written to logic-1.

In the write logic-0 operation shown in FIGS. 42 and 43, hole injection into the floating body region 24 may occur if the emitter-collector voltage of the bipolar transistor 330 a is larger than its emitter-collector breakdown voltage and reduces the efficiency of the write logic-0 operation. In another embodiment of the write logic-0 operation, the following bias conditions are applied: a negative voltage is applied to the selected BL terminal 74, zero or negative voltage is applied to the selected WL terminal 70, zero voltage is applied to the SL terminal 72, zero or positive voltage is applied to the selected BW terminal 76, and zero voltage is applied to the selected substrate terminal 78; while zero voltage is applied to the unselected SL terminal 72, BL terminal 74, and substrate terminal 78, zero or negative voltage is applied to the unselected WL terminal 70, and zero or positive voltage is applied to the selected BW terminal 76. Because the emitter-collector breakdown voltage of the bipolar transistor 330 b is higher than that of bipolar transistor 330 a, no (or significantly lower) impact ionization and hole injection into the floating body region 24 occur.

Memory cells 50, 50G, 150, 250, and 350 can also be constructed in a three-dimensional structure for example having FinFET structures.

FIGS. 44A-44B and FIGS. 45A-45C illustrate reference memory cells 450R1 and 450R2, respectively, which have been described by Widjaja in U.S. application Ser. No. 13/244,899, “Asymmetric Semiconductor Memory Device Having Electrically Floating Body”, which is hereby incorporated herein, in its entirety, by reference thereto. Reference memory cells 450R1 and 450R2 comprise sense line region 20 having the same conductivity type as that of floating body region 24. The sense line region 20 allows for an Ohmic connection to the floating body region 24. Reference memory cells 450R1 and 450R2 may also comprise buried well regions 22G having a lower band gap materials (such as illustrated in memory cell 50G shown in FIG. 19), or having different regions comprising the floating body region 24 (such as regions 24 a, 24 b, and 24 c of memory cell 150 shown in FIG. 20A), halo regions 17 and 19 (such as memory cell 250 shown in FIG. 32A or FIG. 32B), or having asymmetric source and drain regions (such as memory cell 350 shown in FIG. 34).

FIG. 46 shows an exemplary memory array 80 comprising a plurality of memory cells 50 along with a row of reference cells 450R1. Although only one row of reference cells 450R1 is shown, it is understood that memory array 80 may comprise multiple rows of reference cells 450R1, which may be located adjacent to each other or located separate from each other. Similarly, rows of reference cells 450R1 may be located at the edge of the array 80, or in the middle of the memory array 80, or otherwise intermediate of rows of memory cells 50.

FIG. 47 shows an exemplary memory array 80 comprising a plurality of memory cells 50 along with a column of reference cells 450R2. Although only one column of reference cells 450R2 is shown, it is understood that memory array 80 may comprise multiple columns of reference cells 450R2, which may be located adjacent to each other or located separate from each other. Similarly, columns of reference cells 450R2 may be located at the edge of the array 80, or in the middle of the memory array 80, or otherwise intermediate of columns of memory cells 50.

From the foregoing it can be seen that a memory cell comprising a floating body transistor has been described. While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed.

While the present invention has been described with reference to the specific embodiments thereof, it should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation, material, composition of matter, process, process step or steps, to the objective, spirit and scope of the present invention. All such modifications are intended to be within the scope of the claims appended hereto. 

1-29. (canceled)
 30. A semiconductor memory array comprising: a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes: a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with said floating body region; and a back-bias region configured to maintain a charge in said floating body region; wherein said first region, said floating body region, and said back-bias region form a bipolar transistor where the product of forward emitter gain and impact ionization efficiency of said bipolar transistor approaches unity; wherein said back bias region is commonly connected to at least two of said memory cells, and wherein said back bias region has a lower band gap than said floating body region.
 31. The semiconductor memory array of claim 30, wherein said back-bias region is configured to generate impact ionization when the memory cell is in one of said first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states.
 32. The semiconductor memory array of claim 30, wherein each said semiconductor memory cell further comprises a second region in electrical contact with said floating body region and spaced apart from said first region.
 33. The semiconductor memory array of claim 30, wherein each said semiconductor memory cell further comprises a gate region positioned above said floating body region.
 34. The semiconductor memory array of claim 30, further comprising a substrate region, wherein said back-bias region is positioned between said substrate region and said floating body region.
 35. The semiconductor memory array of claim 30 wherein said first and second states are stable states.
 36. The semiconductor memory array of claim 30, wherein said floating body region comprises first and second subregions, wherein said first subregion has a first doping concentration level and said second subregion has a second doping concentration level, and wherein said first doping concentration level is different from said second doping concentration level.
 37. The semiconductor memory array of claim 30, comprising a fin structure extending from a substrate.
 38. A semiconductor memory array comprising: a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes: a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and a back-bias region located below said floating body region; wherein said back-bias region acts as a collector region of a bipolar transistor that maintains the state of said memory cell and has a lower band gap than said floating body region, and wherein said back bias region is commonly connected to at least two of said memory cells.
 39. The semiconductor memory array of claim 38, wherein said first and second states are stable.
 40. The semiconductor memory array of claim 38, wherein a product of forward emitter gain and impact ionization efficiency of said bipolar transistor that maintains the state of said memory cell approaches unity when said memory cell is in one of said first and second states, and wherein impact ionization, when said memory cell is in the other of said first and second states is less than the impact ionization when said memory cell is in said one of said first and second states.
 41. The semiconductor memory array of claim 38, wherein current flow through said bipolar transistor is larger when said memory cell is in one said first and second states than when said memory cell is in the other of said first and second states.
 42. The semiconductor memory array of claim 38, wherein said memory cell states are maintained through impact ionization.
 43. The semiconductor memory array of claim 38, wherein said back-bias region is configured to generate impact ionization when the memory cell is in one of said first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states.
 44. The semiconductor memory array of claim 38, comprising a fin structure extending from a substrate.
 45. A semiconductor memory array comprising: a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes: a floating body region storing a charge or lack of charge indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions; a back-bias region commonly connected to at least two of said memory cells, wherein said back bias region has a lower band gap than said floating body region; and wherein when a first memory cell of said at least two of said memory cells is in a first state and a second memory cell of said at least two of said memory cells is in a second state, application of a back bias via said back-bias region generates impact ionization in one of said first and second memory cells, and not in the other of said first and second memory cells.
 46. The semiconductor memory array of claim 45, further comprising a substrate region, wherein said back-bias region is positioned between said substrate region and said floating body region.
 47. The semiconductor memory array of claim 45, wherein said floating body region comprises first and second subregions, wherein said first subregion has a first doping concentration level and said second subregion has a second doping concentration level, and wherein said first doping concentration level is different from said second doping concentration level.
 48. The semiconductor memory array of claim 45, where said first and second states are stable states.
 49. The semiconductor memory array of claim 45, comprising a fin structure extending from a substrate. 